With the development of mobile communication industry, the demand of high performance and small size electronic devices is also growing. The integrated circuits using compound semiconductor heterojunction bipolar transistors (HBTs) have been widely used in the mobile communication electronic devices for their high power, low noise, and small size. Therefore, by improving the performance and reducing the size of a compound semiconductor HBT circuit will increase the competitiveness of the product.
By applying the conventional flip-chip technology to the HBT device packaging, the emitter copper pillar can be disposed on the emitter electrode of the HBT to improve the heat dissipation efficiency of the device, and the collector copper pillar and/or the base copper pillar are disposed by employing the conventional metallization technology. However, there is a minimum distance between copper pillars in the conventional flip-chip technology, which limits the minimum die size and creates wasteful space between copper pillars, and therefore the competitiveness of the product is restricted. Besides, there is usually a great height difference between the emitter and the collector epitaxial layers, which leads to low uniformity of the height of the copper pillars formed on the emitter and collector electrodes of the HBT. The low uniformity of height of the copper pillars leads to bad contact of the device after packaging, which therefore restricts the packaging yield.